{"id":128,"date":"2013-10-17T16:58:38","date_gmt":"2013-10-17T13:28:38","guid":{"rendered":"http:\/\/profs.hsu.ac.ir\/mbnejad\/?page_id=128"},"modified":"2013-10-17T16:58:38","modified_gmt":"2013-10-17T13:28:38","slug":"vlsi","status":"publish","type":"page","link":"https:\/\/staff.hsu.ac.ir\/mbnejad\/courses\/vlsi\/","title":{"rendered":"VLSI Circuit Design"},"content":{"rendered":"<address>Lecture\u00a0\u00a0 1:\u00a0Introduction<\/address>\n<address>Lecture\u00a0\u00a0 2:\u00a0Manufacturing<\/address>\n<address>Lecture \u00a0 3:\u00a0VLSI Design Technique<\/address>\n<address>Lecture \u00a0 4:\u00a0Devices<\/address>\n<address>Lecture \u00a0 5:\u00a0Transient Response<\/address>\n<address>Lecture \u00a0 6:\u00a0Wire and Interconnect<\/address>\n<address>Lecture \u00a0 7:\u00a0Power Consumption\u00a0<\/address>\n<address>Lecture \u00a0 8:\u00a0Delay and Logic Effort\u00a0<\/address>\n<address>Lecture \u00a0 9:\u00a0CMOS Logic<\/address>\n<address>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022Complementary Logics<\/address>\n<address>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022Ratioed Logic<\/address>\n<address>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022Switched Logic<\/address>\n<address>\u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 \u2022Dynamic Logic<\/address>\n<address>Lecture 10:\u00a0Sequential Logic\u00a0<\/address>\n<address>Lecture 11:\u00a0Noise<\/address>\n<address>Lecture 12:\u00a0Power Distribution<\/address>\n<address>Lecture 13:\u00a0Signaling<\/address>\n<address>Lecture 14:\u00a0Timing<\/address>\n<address>Lecture 15:\u00a0Memory<\/address>\n<address>Lecture 16:\u00a0Adder<\/address>\n<address>Lecture 17:\u00a0FPGA<\/address>\n","protected":false},"excerpt":{"rendered":"<p>Lecture\u00a0\u00a0 1:\u00a0Introduction Lecture\u00a0\u00a0 2:\u00a0Manufacturing Lecture \u00a0 3:\u00a0VLSI Design Technique Lecture \u00a0 4:\u00a0Devices Lecture \u00a0 5:\u00a0Transient Response Lecture \u00a0 6:\u00a0Wire and Interconnect Lecture \u00a0 7:\u00a0Power Consumption\u00a0 Lecture \u00a0 8:\u00a0Delay and Logic Effort\u00a0 Lecture \u00a0 9:\u00a0CMOS Logic \u00a0 \u00a0 \u00a0 \u00a0 \u00a0 <a class=\"more-link\" href=\"https:\/\/staff.hsu.ac.ir\/mbnejad\/courses\/vlsi\/\">Continue reading <span class=\"screen-reader-text\">  VLSI Circuit Design<\/span><span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":20,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"template-onecolumn.php","meta":{"footnotes":"","_links_to":"","_links_to_target":""},"class_list":["post-128","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/pages\/128","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/comments?post=128"}],"version-history":[{"count":0,"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/pages\/128\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/pages\/20"}],"wp:attachment":[{"href":"https:\/\/staff.hsu.ac.ir\/mbnejad\/wp-json\/wp\/v2\/media?parent=128"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}